CML Termination Design

They're flaring gas and using diesel to fuel the pumps—it's like something Homer Simpson would do.

— North Dakota cattle rancher Vawnita Best, after seeing natural gas being flared off of wells on her property for over a year. She was simply appalled at the waste.

Figure 1: Termination Circuit.

Figure 1: Termination Circuit.

An engineer stopped by today and had forgotten how to use Mathcad to solve a pair of circuit equations to determine termination resistor values. I stepped in and helped. As I looked at the problem, I thought this might be useful to cover here as a tool demonstration.

I continue on my quest to show the usefulness of computer-algebra systems to masses. Depending on the problem at hand, I use either Mathcad or Mathematica. You only see Mathcad on this blog because I generally write on my lunch break and we only have Mathcad at work. I actually love to work with both tools, but Mathcad is better for quick calculations – it was born as an engineering tool.

Figure 1 shows the circuit in question. This circuit may look a bit strange, but it reflects the differential nature of Current-Mode Logic (CML).

We have the following requirements for this circuit:

  • V1=3.295 V
  • V2 = 1.2 V
  • VT = 1.2 V
  • RT = 50 Ω
  • R1 and R2 are related to RT by the following equation
    R_T={{R}_{1}}+\frac{1}{{\frac{1}{{{{R}_{2}}}}+\frac{1}{{{{R}_{T}}}}}}

Our mission is to select values for R1 and R2 to meet these requirements. Figure 2 shows the Mathcad solution I wrote out in less than a minute. I directly wrote out Kirchoff's voltage equations in Mathcad with no thinking. I then let Mathcad solve the system.

Figure 2: First Solution, No Thinking.

Figure 2: First Solution, No Thinking.

If this were my design, I would finish off the calculation by selecting standard resistor values. I have a Mathcad program that does that for me. For this situation, the engineer working on the circuit will select the final part values.

As I thought about the circuit, I did not need to write such a complex equation for V2. Since VT = V2, no current is flowing through RT. This means I can write a simpler set of circuit equations that provide me the same solution, which I show in Figure 3. As expected, I get the same results.

Figure 2: Simpler Approach Using Circuit Insights.

Figure 3: Simpler Approach Using Circuit Insights.

My intent here is just to illustrate how useful these tools are in an engineer's daily life. I rest my case.

Postscript

The engineer that I worked with on this problem sent me his lab results. This may not mean much to most of you, but the testing verified that our modeling worked as expected. We have a properly terminated signal with the correct levels.

Figure M: Confirmation in the Lab.

Figure 4: Confirmation in the Lab.

 
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One Response to CML Termination Design

  1. Pingback: Yet Another FPGA Differential Termination Example | Math Encounters Blog

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