Quote of the Day
This is not a peace. It is an armistice for twenty years.
— Ferdinand Foch on WW1's Treaty of Versailles in 1919. He proved to be prophetic, with WW2 starting almost twenty years to the day after he made this statement.
Introduction
Figure 1: My Proposed Differential Termination Network. It is drawn in LTSpice. In a later post, I will discuss how to use LTSpice to solve this problem.
An engineer asked me for assistance on determining the termination circuit for a Xilinx uG476 series 7 FPGA. The circuit works is slightly different manner than those termination circuits I have developed before (here and here) because there is not termination voltage, so I thought I should document my work here in detail. I will be using Mathcad 15 to determining the optimal resistor values for (1) terminating the circuit in printed circuit board's characteristic impedance (Z0), and (2) ensuring that I preserve as much of the transmit signal level as possible without exceeding the input circuit's maximum voltage level.
This is a classic optimization problem that engineers must solve on a regular basis. I have been working on many of these problems lately, including a factory optimization problem that I will be documenting in a future post.
For those who are interested, my Mathcad source is here.
Background
Definitions
- Common-Mode Voltage (VA and VB)
- This is the DC level of the differential signal. In the circuit of Figure 1, there are two common-mode voltage requirements that must be met: (1) the open-circuit output voltage for the transmitter (VA), and (2) the open-circuit voltage for the receiver (VB).
- Characteristic Impedance (Z0)
- For the low-loss case we have here, the characteristic impedance is the resistive value that represents the effective resistance of an infinitely long transmission line.
- Gain (G)
- Really, this is an attenuation factor between the differential signal (represented by V3 and V4 in Figure 1, and the signal across the termination resistors, R5 and R6. Xilinx refers to this parameter as "Gain," and I will use their nomenclature.
Requirements
The requirements are simple:
- VA = 1.3 V (specified by Xilinx)
- VB = 0.8 V (specified by Xilinx)
- R5, R6 = 50 Ω (inside the FPGA and specified by Xilinx)
- 0.267 ≤ G ≤ 0.813 (see Appendix A for details)
Analysis
Circuit Formula Derivation
Figure 2 shows how I derived the formulas for the resistor values required to meet the Z0 and common-mode voltage values, which are met exactly by these formulas.
Figure 2: Derivation of Resistance Formulas.
Solution for Resistance Values
Figure 3 shows how I used Mathcad's maximize routine to determine the optimal resistor values. I chose the resistor values to find the largest gain consistent with the gain range limits.
Figure 3: Determine the Optimum Solution.
This solution shows that R2 is large relative to the other resistors and can be replaced by an open circuit.
Solution for Resistance Values
Figure 4 shows how I converted the computed resistor values to standard resistor values. I also verified that my solution is still valid using standard resistor values (see Appendix B).
Figure 4: Compute Standard Resistance Values and Double Check the Solution Still Works.
As mentioned above, R2 is so large relative to the other resistances that it can be replaced by an open circuit. All requirements are met by the computed resistance values.
Conclusion
I was able to derive the required resistor values to meet the requirements that Xilinx imposed on the termination. This circuit will be used for terminating electronics within a high-speed fiber optic product.
P.S.
I have been working in Aveiro, Portugal for the last week. The circuit was tested in my absence and worked.
Appendix A: Gain Requirements.
Figure 5 shows how Xilinx derived the gain requirements here.
Figure 5: Derivation of Gain Margin Min and Max
Appendix B: Determining Closest Standard Resistor Value.
Figure 6 shows my routine for determining the closest standard resistor value to the computed resistor value.
Figure 6: Determining Closest Standard Resistor Value.
What's to stop the circuit from over driving itself. certainly the noload/load transition would be too fast to prevent circuit failure. and if vcc1 and vcc2 are biased, wouldn't that increase the peak-to-peak voltage ratio to 6.6 v minus any voltage drop. wouldn't a diode or bridge rectifier help ?. I just don't see any line feedback in your drawing to help prevent such an event.
I am computing the required termination values. The circuit designer will be adding any required protection circuitry. My intent here is to show how to determine the resistors that provide the correct bias, gain, and characteristic impedance values.
mark
Sorry, I overlooked your initial objective. I agree with your calculus to determine impedance values, but to simplify, as you know, circuits can be classified as serial and/or parallel in relationship to source and drain which i do not see in your diagram. So is this an isolated circuit ?
It is an isolated circuit.
mark
Why MathCad? Why math equations so the work can be shown?
You bring up a good point – there are a number of ways to solve this problem. I use Mathcad because:
Most of my staff does not use Mathcad – they prefer to use Excel and LTSpice. To support these engineers, I also have termination solutions using Excel and LTSpice. I will post those in the next few weeks so that folks can understand how to work these problems using different tools.
I should mention that Xilinx used an iterative approach, which is also a valid method. However, it is a difficult method to use when you want to ensure an optimal solution.
mark
Well i feel stupid, guess i should have read the tech doc on 'Xilinix uG476 series 7 FPGA' before commenting. their published specs call for single end voltage for Vise. with your design it should provide a stable voltage across ramp current.